module WB(CLK, reset,
	  reg_wen_in, reg_wen_out,
	  wb_sel_in, wb_sel_out,
	  reg_waddr_in, reg_waddr_out,
	  aluresult_in, aluresult_out,
	  memoryout_in, memoryout_out
	  );

   input CLK;
   input reset;
   input reg_wen_in;
   reg   reg_wen;
   output reg_wen_out;
   assign reg_wen_out = reg_wen;

   input  wb_sel_in;
   reg    wb_sel;
   output wb_sel_out;
   assign wb_sel_out = wb_sel;

   input [4:0] reg_waddr_in;
   reg [4:0]   reg_waddr;
   output [4:0] reg_waddr_out;
   assign reg_waddr_out = reg_waddr;

   input [32:0] aluresult_in;
   reg [32:0]   aluresult;
   output [32:0] aluresult_out;
   assign aluresult_out = aluresult;

   input [31:0]  memoryout_in;
   reg [31:0]    memoryout;
   output [31:0] memoryout_out;
   assign memoryout_out = memoryout;

   always@(posedge CLK or posedge reset)
     begin
        if (reset) begin
           reg_wen <= 0;
	   wb_sel 	<= 0;
	   reg_waddr<=0;
	   aluresult <= 0;
	   memoryout <= 0;
        end else begin
	   reg_wen <= reg_wen_in;
	   wb_sel 	<= wb_sel_in;
	   reg_waddr<=reg_waddr_in;
	   aluresult <= aluresult_in;
	   memoryout <= memoryout_in;
        end
     end


endmodule
